E20-385 exam Dumps Source : E20-385 Data Domain Specialist for Implementation Engineers
Test Code : E20-385
Test name : E20-385 Data Domain Specialist for Implementation Engineers
Vendor name : EMC
: 207 actual Questions
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EMC Corp. and NetApp battled for six weeks over facts district Inc., a number one enterprise in data deduplication technology. NetApp positioned an customary tender on statistics district for $1.5 billion on may additionally 20. quickly after, EMC challenged that bid, and the two businesses went back and forth in their offers for a pair of weeks, except July 6, when EMC placed the highest bid of $2.1 billion. NetApp stepped down from the bidding warfare on July 8, and records domain approved EMC's present of $2.1 billion. they Have now compiled their plenary coverage of the EMC/statistics domain/NetApp battle, expert guidance, podcast interviews, and their foremost supplies on records deduplication.
EMC/records domain/NetApp: table of contents
EMC/data domain/NetApp advice coverageEMC/statistics domain/NetApp podcasts information deduplication technology substances
EMC/statistics domain/NETAPP exclusive information insurance
EMC acquires records district for $2.1B after NetApp drops bidEMC wins the combat over data domain. NetApp pointed out it will no longer boost its bid to purchase the facts deduplication backups specialist, and facts domain's board authorized the $2.1 billion tender EMC made July 6 and entered birthright into a definitive agreement.
EMC raises its acquisition tender for information deduplication vendor information district to $2.1BEMC raised the stakes in its bidding battle for statistics deduplication backup professional information district Inc., increasing its any money tender to $33.50 per share or $2.1 billion in an attempt to sway the information district board from accepting NetApp's present of $1.9 billion.
Storage trade weighs EMC's, NetApp's bidding warfare for facts DomainStorage directors maintain an in depth eye on EMC's and NetApp's bidding struggle for statistics district Inc. after NetApp raises the bid to $1.9 billion, and marvel how the destiny of the information deduplication backup specialist will Have an repercussion on the storage business.
EMC wants to purchase statistics district for $1.eight billion to dominate data deduplication marketEMC provided $1.eight billion to purchase information area, eclipsing NetApp's $1.5 billion present for the target-based mostly deduplication backup specialist on may furthermore 20.
NetApp plans to purchase statistics deduplication professional facts district for $1.5 billionNetApp Inc. made a daring bound to develop into the market chief in facts deduplication technology when it obtained statistics domain Inc. for $1.5 billion in a blended cash and inventory transaction.
PODCASTS ON EMC/NETAPP/records domain: professional belief AND analysis
EMC continues the battle for information district with unusual bid of $2.1 billionThe bidding battle between EMC and NetApp over statistics district persisted as EMC raised the bid to a noteworthy money tender of $2.1 billion. Beth Pariseau, senior advice writer at SearchStorage.com, and Curtis Preston, government editor at TechTarget, talk about the latest traits of the anecdote during this podcast.
EMC and NetApp proceed the battle over information DomainEMC raised the bid to $1.eight billion. Beth Pariseau, senior information author for SearchStorage.com, talks in regards to the merits of having statistics domain in a company, and what this deal may affect for the longer term. And Curtis Preston, government editor at TechTarget and impartial backup professional, talks about the battle between EMC and NetApp.
records DEDUPLICATION substances: THEIR properly five facts DEDUPE suggestions
statistics deduplication can hold organizations time and cash by means of enabling extra information healing from disk and cutting back the footprint and vigour and cooling requirements of secondary storage. live mindful where and how to utilize statistics deduplication know-how in disk-based mostly backup listed here.
if you've decided that your information backup device can profit from data deduplication, you really Have a variety of choices. during this tutorial, they examine publish-processing versus inline deduplication, disk-based mostly backup and dedupe, and compare the well-known deduplication products. live trained every miniature thing you should know about deduplication in their statistics deduplication tutorial.
statistics deduplication is one of the hottest technologies in data backup and healing. however before you achieve into result a deduplication product, you'll want to faith even if it gives world deduplication. live taught why global deduplication is censorious in this tip.
statistics deduplication ratios may furthermore live very complicated. find out about how to estimate a data deduplication ratio on your backup materiel and the artery to reckon a dedupe product. you will furthermore live trained what's a practical data dedupe ratio to are expecting from a backup product listed here.
statistics deduplication is longer a bleeding-part know-how, and the cost ticket downs of statistics reduction is chiefly attractive as agencies contend with information boom and tightening budgets. SearchDataBackup.com requested clients concerning the deduplication products they've deployed, and the professionals and cons of every. study information deduplication approached in backup nowadays.
crimson Hat Inc. is bolstering its storage product portfolio with the acquisition of Permabit expertise Corp.’s know-how belongings, the commercial enterprise Linux company revealed Monday.
The settlement will additionally perceive sixteen of Permabit’s employees link purple Hat. terms of the deal were now not disclosed.
centered returned in 2000 with a total of $12 million in chore capital funding behind it, Permabit has through the years managed to carve out a gap for itself as a professional in what it calls “information effectivity expertise.” extra especially, it presents items that allow agencies to lucid up their company data a pleasant artery to access it quicker and rescue it greater efficaciously. It furthermore sells statistics compression technology. in addition, the enterprise has partnered with pink Hat considering the fact that 2016 to live positive its utility works with the latter’s storage items.
In a statement, crimson Hat famed the addition of Permabit’s statistics deduplication and compression applied sciences should live a fine lucky for its personal storage offerings. “With the addition of Permabit’s statistics deduplication and compression tools to pink Hat business Linux, purple Hat could live ready to aid these companies as they are searching for to derive a greater efficient storage footprint,” famed Jim Totton, a red Hat vice chairman and accepted manager.
The acquisition should as a minimum get crimson Hat’s storage products greater appealing. information storage is cheap however it nonetheless comes at a cost, and people fees achieve add up for companies transitioning to greater expensive but more suitable-performing flash storage. This identical common sense become additionally pointed out to live the incentive at the back of EMC Corp.’s $2.four billion acquisition of statistics domain Corp., yet another enterprise that cleans records, again in 2009.
crimson Hat observed the deal will “have no fabric Have an repercussion on” on its 2nd-quarter or fiscal-yr profits.image: Jared Smith/Flickr considering you’re birthright here …
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SAN ANTONIO--(enterprise WIRE)--Rackspace® internet hosting (NYSE: RAX), the provider chief in cloud computing, today announced it will extend its relationship with EMC through joining the EMC velocity™ carrier company software to boost unusual cloud-primarily based carrier offerings. the two groups Have collaborated given that 2001 to carry a plenary latitude of resourceful options leveraging EMC’s portfolio of counsel infrastructure items including digital storage and various cloud-based information administration services.
“Our conclusion-clients will handicap from the relationship between EMC and Rackspace as it offers the IT options from both agencies on one seamless offering while decreasing charges,” famed Jim Lewandowski, senior vp of global income for Rackspace. “during the past, meeting computing needs intended you needed to buy servers, tap technical talent after which constantly reinvest to sustain with expertise. Now the end-clients can shift their seat of attention to their mission-crucial apps, core expertise and innovation whereas being supported with the aid of their hallmark Fanatical assist.”
With the improved relationship the agencies will work collectively on new, joint solutions in order to enable agencies to optimize efficiencies and reduce expenses. throughout the hurry service company companion application, EMC will work with Rackspace to permit Rackspace to convey a wide variety of cloud-primarily based IT features to the world IT market.
latest service offerings consist of Rackspace managed commercial enterprise deepest Clouds that are based on EMC Symmetrix VMAX™ and EMC VNX™ unified storage to deliver business storage enviornment networks. moreover, Rackspace provides statistics replication capabilities based on EMC RecoverPoint, EMC information area®, and EMC Isilon® items. Rackspace furthermore presents EMC options with Fanatical guide®, giving end-clients a much wider option of cloud-primarily based IT options and tactical advantages equivalent to cost reductions, flexibility and scalability coupled with world-classification steer to enhance its efficiency.
“As long time companions, the expansion of their relationship to develop unusual cloud-based solutions is a herbal evolution. Rackspace’s rock solid basis and world category Fanatical assist mixed with EMC’s portfolio of products that are optimized for digital environments will enable Rackspace to bring inventive cloud computing offerings,” famed EMC’s Dennis Hoffman, Senior vice president, carrier suppliers. “EMC is dedicated to working with carrier providers relish Rackspace to convey trusted, enterprise-class cloud features that permit their mutual purchasers to choose the redress source for each IT workload.”
About Rackspace hosting
Rackspace hosting is the world’s leading professional in the internet hosting and cloud computing business, and the founding father of OpenStack™, an open source cloud platform. The San Antonio-based enterprise gives Fanatical assist® to its purchasers, across a portfolio of IT services, including Managed hosting and Cloud Computing. Rackspace has been diagnosed by artery of Bloomberg BusinessWeek as a desirable 100 Performing know-how company and turned into featured on Fortune’s record of 100 most profitable agencies to work For. The company become additionally located in the Leaders Quadrant via Gartner Inc. in the “2010 Magic Quadrant for Cloud Infrastructure as a service and internet hosting.” For greater guidance, discuss with www.rackspace.com.
EMC, pace, Symmetrix VMAX, VNX, facts district and Isilon are registered logos or logos of EMC corporation or its subsidiaries within the u.s. and different countries.
This press unencumber carries ahead-searching statements that hold dangers, uncertainties and assumptions. If such hazards or uncertainties materialize or such assumptions prove wrong, the outcomes of Rackspace internet hosting could range materially from these expressed or implied with the aid of such forward-looking statements and assumptions. any statements other than statements of ancient fact are statements that may well live deemed forward-searching statements, including any statements regarding anticipated construction, efficiency or market acceptance linked to their product choices and services, including those provided with the aid of EMC; anticipated operational and fiscal advantages from their product choices and capabilities, including those supplied through EMC; any statements of expectation or belief; and any statements of assumptions underlying any of the foregoing. risks, uncertainties and assumptions encompass the probability that anticipated advantages from their product offerings and capabilities may furthermore now not materialize as a result of their products don't look to live frequently authorised within the industry, which may spin up as a result of positive components including (i) a failure to market the product or functions can impregnate with no trouble, differentiate the product from competitive products or communicate differentiations effortlessly, (ii) the reliability, first-class or compatibility associated with their products and services, (iii) changes in technology which adversely affect the benefits of their products or functions, and (iv) other dangers that are described in Rackspace internet hosting's profile 10-Q for the quarter ended June 30, 2011, filed with the SEC on August 8, 2011. except as required by using legislation, Rackspace hosting assumes no responsibility to replace these ahead-looking statements publicly, or to replace the motives actual outcomes might fluctuate materially from those predicted in these forward-looking statements, although unusual assistance turns into accessible in the future.
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Simulation and analysis (S&A) are not known for its simplicity. It has traditionally been the domain of experts. The problems they encounter are theoretically complex, and the software used reflects this complexity.
Nevertheless, S&A has become a key district of product development. This raises questions like: How can it live made easier? How can they spread the utilize of these tools to a wider fraction of the product design community? And, can simulation process and data management (SPDM) embolden to democratize S&A?
A broader user base. Commercial SPDM solutions are only in utilize by less than five percent of simulation specialist engineers in mainstream companies. But with easy-to-use apps that contain, among other things, embedded simulation expertise, there is plight of a viable broadening of the user base.
Let us celebrate at simulation with a focus on SPDM. The adoption of SPDM within mainstream product progress has, according to CIMdata, “been extremely disappointing from a business repercussion perspective.”
According to the analyst, fewer than five percent of any simulation specialists worldwide utilize some profile of commercial simulation data management technology to manage and archive their simulation models and to collaborate with other simulation specialists and design disciplines within their organizations. With this in mind, a broader utilize of simulation tools and results can become powerful support for Important advances in the utilization of modern product progress technology
Although there are exceptions, simulation software is generally not easy to use, share, or, for that matter, even understand for some members of product progress teams. At the identical time, the capabilities of the software and the results are necessary to understand the physical conduct of designs and to validate their functionality, strength, motion in a flow, etc., as well as fill regulatory requirements. This does not affect that they’re not useful for less involved simulations. But in general, their overall result has been bottlenecks in the product design process, making for a longer time to market, and a longer wait before revenues start rolling in.
Can the tools and processes become more useful not only for the analysts, but also in the broader "designer collective" in this progress chain's increasingly Important link?Process Templates Are Not the Answer
Gartner Group's PLM analyst and vice president, Marc Halpern, was one of the first employees of the now market-leading CAE software developer ANSYS.
Gartner's PLM analyst and vice president, Marc Halpern, has a solid background in simulation and analysis. He was one of the earliest employees in ANSYS, the leading simulation software vendor. There is of course more than one solution to the democratization of simulation software, he notes, but an gripping aspect that is sometimes heard in the discussions is: "Democratize CAE with SPDM (simulationprocess and data management)." But can SPDM really democratize CAE? Both yes and no, says Halpern:
“I Have always understood SPDM as a artery to manage models and results. A separate CAD model can live used to create many different models to execute many different simulations. Although simulation models and data are managed perfectly, this in and of itself does not affect that CAE becomes more democratic. Not even the ‘process templates’ can decipher the basic problem,” Halpern claims, pointing to things relish common self-confidence in the results.
“Does the model used match reality so that the results become useful? Another Important point is about the interpretation of the results, which can live a problem.”
On the other hand, Halpern says that there are promising examples of embedded expert learning and methods in SPDM solutions, pointing at (Aras-owned) Comet’s SimApps. “I believe this is what differentiates what Aras is selling from what I typically perceive from SPDM technology,” he said.
Though the concept of simulation with pleasant SPDM has been recognized as having a lot of potential, the adoption of SPDM solutions has been an “extreme disappointment", as CIMdata formulates it.
The emergence of simulation as a key technology can live seen in reduced utilize of physical prototypes. Simulation and analysis tools can replace a physical prototype with its digital version. Products that only exist virtually must live tested and validated before they are produced. Not only that, in the era of mass individualization, a big number of variations can produce families of products or parts, and they any Have to work.
With a connected product (IoT), the operation of a product will furthermore generate usage data and information about the part’s environment and operating conditions.ERP is Immediate ROI, SPDM is Long-Term
As a result of these trends and unusual technologies, the number of simulations has increased dramatically in the last decade, reflected in the growth of investments in simulation and analysis tools.
According to CIMdata, this growth has made simulation the “star” of the PLM industry, with annual growth rates of around 10 percent over each of the past five years. They Have thus furthermore achieved an mediocre growth substantially higher than other PLM investments (CAx, ALM, cPDm etc.) during the identical period.
In 2017, investments into simulation software and service investments were worth $5.5 billion, making up 13 percent of the total of the PLM investments.
So, how has this prolific climate affected the growth of SPDM? While CIMdata states "the end-user's interest in SPDM has increased significantly over the past decade," increased interest has not caused increased implementation. CIMdata voices "an extreme disappointment" over the behind industrial uptake of SPDM, at least outside the major automotive and aerospace industry’s OEM companies.
But Halpern is not surprised. “There are pleasant reasons for this [slow uptake]. In stark contrast to ERP investments—which provide immediate cost-saving effects that are directly reflected in the profile of profits and rising share prices—SPDM investments are more likely to provide long-term positive effects, which are more difficult to detect immediately. SPDM can get engineers more productive in a artery that, from management's point of view, does not Have the short-term, immediate benefits that ERP provides,” explains the Gartner analyst. Since so few senior executives understand SPDM, they can’t really champion it. SPDM is not like product design, sourcing and manufacturing operations, where what can proceed wrong can live quite obvious, cause delays in the delivery of the product, and affect the company’s bottom line.
They know that construction and technology are important, Halpern adds, but the "pain points" and the consequences of design engineering are often "too far over the horizon” for executives.
“Therefore, most of the champion for SPDM ventures generally comes from engineering teams, and the simulation teams in particular. It doesn’t embolden that SPDM is difficult to implement—as difficult, if not more, than PDM. any in all, this is the understanding I can perceive behind the behind growth in SPDM.”
Again, the situation is not encouraging.
"The actual adoption rate within mainstream product progress activities has been extremely disappointing from a business repercussion perspective... Unfortunately, the most common profile of SPDM in exercise today is noiseless the utilize of personal hard disk storage on the simulation engineer’s desktop or perhaps a shared drive used in common with other members of their immediate organization. Naming and versioning of simulation models and results is haphazard at best and totally inconsistent in the worst cases. This makes the traceability and pedigree of simulation models and results extremely difficult, if not impossible, to accomplish and can lead to a necessity of self-confidence in the accuracy of the simulation results versus physical test data," CIMdata writes in the 2018 release of its Simulation & Analysis Market Analysis Report.
Nevertheless, thereare some positive signs which point to a possibly larger utilization.
“The actual value of SPDM from a democratization perspective is that, after all, there are tools that enable experts to package the learning that can live linked to a design model in a artery that makes it viable for many designers without advanced simulation learning to grasp fraction of, and even do, simulations,” says Halpern.Turning Months into Days
One company that has SPDM platforms to its handicap is Boeing. By tying together simulation and process data, Boeing manages to abbreviate some progress processes substantially.
This goes well in line with other cases where progress processes Have been shortened from months to days. In extreme cases—when the redress knowledge, interpretation and the redress simulation results are any embedded in the design model—the progress process can live shortened to hours.
This proves SPDM solutions can live a key to success when the utilize of simulation tools is constantly growing—with the caveat that they are not only used in “normal" design processes, but furthermore in later phases: during the product realization process, as well as when products are in use.
More and more PLM vendors are furthermore starting to celebrate at packaging and developing solutions that get simulation more accessible to multiple stakeholders in product development teams. It’s common learning that there is a gap and that the claim for bridging the gap is on the rise. Sweden-based multiphysics software vendor, COMSOL (with the Application Builder), was early to tender solutions for this, but furthermore the simulation giant ANSYS, MSC and the three PLM majors (Siemens PLM, Dassault and PTC) are now working on broadening their respective platforms’ functionalities related to SPDM. The PLM rocket, Aras, closed the gap between simulation and developmentwhen it acquired Comet Solutions at the suspension of September 2018.
“Much remains to live gained if they can close the gap between simulation and mainstream design by giving simulation analysts the opening to iterate and reuse simulations while connecting the analysis to product configuration and multidisciplinary design through quality of life,” says Marc Lind, senior vice president of Strategy at Aras.
SPDM challenges. The adoption of SPDM solutions is far from a question of technology only. People, processes and company culture, as well as governance play significant roles.SPDM to Understand Product Realization Process
As for the commercial SPDM solutions, CIMdata points at a problem in this context: they Have been developed specifically for 3D modeling and simulation (such as finite component analysis and computational fluid dynamics). This means that they often necessity efficient champion for models and information created in 0D/1D systems modeling, which is censorious when implementing an MBSE (Model-Based Systems Engineering) approach.
However, the major solution providers are now recognizing this necessity and the analyst expects to perceive significant progress in this district over the next several years.
But the low mainstream adoption rate is far from a question of technology alone. People, processes and company culture, as well as governance, play significant roles:
However, software vendors are noiseless in the early days in developing SPDM solutions that are both robust and easy to use.
Most analysts alsoagreethat the exponential growth of CAE and the explosion of simulation-related data appearing from increasing digitization, unusual technologies and disruptive product realization methods requires more competent management systems.
“Without pleasant SPDM tools, it will live difficult to effectively understand this fraction of the product realization process,” says Marc Halpern.
Simulation is an needful component throughout this process. Why?
“SPDM platforms will live crucial to realizing the exact potential of PLM, digital threads and digital twins, and enable collaborations with other corporate platforms, such as ERP, MES and MRO to realize Industry 4.0 concepts in the next step,” Halpern adds.
CIMdata agrees in its 2018 report: "Companies necessity to live better at managing simulation models, results and related design information, improving collaboration and reusing and better integrating simulation activities into the PLM environment. Doing this supports a larger audience of product progress engineers, engineering managers, product managers and others in the extended organization and supply chain who can profit from access to simulation information to get more informed decisions."Halpern concurs, adding, “But there are furthermore elements in the data management, which I observed in my research on digital twins, which applies to SPDM. I perceive a sturdy connection between the digital twin concept and SPDM.”Embedded Knowledge, Disrupting Institutional Silos
CAE is traditionally one of the more well-preserved siloes in product development. But in recent years, they Have seen increased communication between the analysis, simulation and the relaxation of the members of the product progress team. Also, it is lucid that unusual disruptive technology can live a catalyst and is able to rupture up isolated data structures.
But there’s more. Can a software developer create solutions that can meet the unusual requirements to extend collaboration opportunities, Halpern wonders.
Without uncertainty. Is it viable to parameterize the thermal analysis of a microprocessor on a circuit board, so that it can live applied to similar configurations and variations without uncertainties about the mesh?
During a NAFEM presentation, the Gartner analyst said that this is an instance of a capability that one can embed in a model.
“Some call it encapsulation,” Halpern continued. "But whatever you call it, this kindly of encapsulated information can free up engineers from having to live full-time analysts. The specialized terminology, conventions, and features of the simulations can remain under the hood and the interface made considerably easier to use. A involved problem can live solved with a handful of parameters. This would provide simulation to not only engineers, but furthermore to others involved in the product and its design.”Aras Takes a Step with Comet Acquisition
Allowing more engineers to execute simulation is exactly what the PLM developer Aras was aiming for when it purchased Comet. The acquisition is an Important step on a roadmap for developing platform-based SPDM to champion increased utilize of simulation for involved scenarios.
Aras aims to better Innovator’s talent to ply simulation data. With Comet's technologies, manufacturers and product developers can reuse involved simulations to scale up or down the application and widen the utilize of simulation results. One result: it is now viable to connect simulations and gain access to experts in the bailiwick by offering traceability, access and reuse during the product life cycle.
Comet's products are largely based on a string of customer-developed and web-implementable "SimApps," with built-in expert learning and methods. “These SimApps,” says Aras Marc Lind, “create a simulation-driven design that fits any users, from CAE experts to design engineers. "
We question Halpern if this is what he meant by encapsulated knowledge.
“Exactly!” says the Gartner analyst. “This distinguishes what Aras sells from what I usually perceive in terms of SPDM technology.”
He added that Comet's actual value in democratizing simulation is its talent to integrate functionality and learning into CAD models so that the person making the simulation or evaluation necessity not worry about involved problems and intricate trade-offs to get the simulations.
“Encapsulated learning takes impregnate of it."
Web-based Simulation a la Aras. Comet’s SimApps (now fraction of Aras) are web-based simulation programs that are easy to use, even for salespeople. Product engineers can execute involved simulations safely. These SimApps can respond specific questions about the design of a product in a product family, for example. Comet experts, partners and customers Have built, tested, and deployed a comprehensive library of SimApps that capture and execute best practices for simulation, automate repetitive and tedious tasks and secure the power of sophisticated CAE analysis in the hands of both experts and non-expert users.Links Between Users and Non-Experts
An Important point to gather SPDM to work is to apply a "vendor-agnostic" implementation by connecting a wide range of CAD, FEA, meshing, 0D/1D simulation tools and proprietary applications. It is a requirement for supporting the often heterogeneous software environments found in organizations.
Aras's chief architect, Rob McAveney, argues that wider utilize of simulation has generally deteriorated as the simulation process and data management tools (SPDM) necessity efficient links between simulation users and the extended enterprise.
“Expanding the digital thread to involve simulation tools and processes has emerged as an Important factor for future business models,” he says. “Simulation can add significant value to product development, manufacturing and bailiwick operations, but has not yet reached its potential due to limited connection to the relaxation of the company. Through Comet they can capture what is needed to realize the potential: Repeatability, reusability and traceability for simulation across the entire product life cycle”
McAveney sees a market growing exponentially, while progressing as the utilization of physical testing decreases. He furthermore points out that the complexity that comes with smartly connected product design and MBSE are Important trends that will champion the necessity for this kind of platform.
“We perceive simulation in its context, with overall system technology processes together with configuration and change, variants, requirements, validation testing and more. The fact that simulation management is often completely disconnected from mainstream processes is a problem as there is no traceability throughout the product life-cycle loop,” says McAveney.
McAveny points to the import of developing the "digital thread" and solutions with digital twins for predictive maintenance.
"With Comet technology they close the gap between simulation and mainstream design by giving simulation analysts methods to iterate and reuse simulation, link the analysis to product configuration and design during the product life cycle,” he summarizes.
He furthermore points to Comet's talent to ply mixed models, different data types and representations of the identical product. The identical applies to assembly, which furthermore needs to live simulated. any in all, this offers "an Important aspect of managing system simulations across several technical disciplines."
The talent to extract intelligence from simulation models and results, rather than just managing data at file level, is furthermore a broad handicap over other SPDM systems on the market.
What the common setupof ANSYS’s SPDM solution EKM looks like.Others gather into the Act
Aras is not alone. PLM market leaders Siemens and Dassault Systèmes Have invested heavily to beef up their simulation solutions in recent years. ANSYS, PTC, MSC, and others, are working on their own SPDM solutions.
One of the main reasons for this is the claim from customers in industrial segments that are convinced of the power of simulation and SPDM, such as automotive and aerospace."Among those who are early on to pick up SPDM (like BMW), design decisions --or simulations that led to a design conclusion - must live traceable," says Marc Halpern. “The test data management functions that Aras is developing with BMW will live gripping to follow. The combination of SPDM with next generation test data management can lead to exciting insights into system progress that are designed or evaluated.”
Will an SPDM solution embolden them in their efforts? Given the above arguments, it is not unreasonable to expect some kindly of difference. But, selling this kind platform of is not an easy task.
In addition, one should bear in irony the built-in structural resistance in corporate organizations, where the simulation has always been its own department and the controversy for a well-functioning SPDM encounters is countered with the significant costs of its implementation, especially exact at big automotive and aerospace companies.
But for the bottom line, the revert on investment of SPDM looks convincing enough. Even “compelling”, asserts CIMdata in its 2018 report.
Finally, Aras this week announced a partnership with Visual Collaboration Technologies (VCollab) for simulation visualization, post processing, and reporting. Aras will utilize the VCollab technology in SPDM processes across the lifecycle. Worth noting is the fact that VCollab can ply formats from any of the broad simulation developers (ANSYS, MSC, etc.), which makes it easier to spread and understand simulation results in broader product realization teams. This is one of the greatest values with SPDM.
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Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address problems much earlier than in the past.
While power has long been a major focus in the mobile space, power-related issues now are spreading well beyond phones and laptop computers. There are several reasons for this:
These challenges extend from data centers, where AI, networking, and telecommunications require massive amounts of energy, any the artery to the edge. At 7nm, it’s not uncommon for chips to live large, sometimes at reticle size, with hundreds or thousands of processor cores. But unlike in the past, where those processors were mostly murky except for required bursts of activity, some of the unusual application areas require more of these processing elements to live on more often, if not any the time.
And this is where problems such as heat, electromigration, power-related uproar and reliability become particularly difficult to manage.
“CPU Utilization, power management and device reliability must live tightly and accurately thermally managed on die,” said Stephen Crosher, CEO of Moortec. “Otherwise, data seat electricity bills can live millions of dollars higher than necessary each year. Datacenter operators are now seeing the direct correlation between site-running costs and the thermal monitoring and management adopted artery down profound within the system at chip level.”
This is driving unusual techniques such as real-time, in-chip thermal guard-banding to enhance the implementation of health monitoring, failure prediction and the design of higher rack density configurations. But in many cases the solutions are just barely keeping pace with the problems. Everyone wants to utilize AI/ML/DL in a chip, whether those chips are used inside data centers or at the edge, but the multiply/accumulate processing consumes a lot of energy.
“Whether you’re doing that to a specialized CNN block, as in the case of embedded vision processes, or whether you’re doing it in a graphics chip with GPUs, it’s any about multiply accumulates,” said Yudhan Rajoo, technical marketing manager for foundation IP at Synopsys. “The artery they deal with this problem is primarily after the RTL has been written, by instantiating inevitable involved cells in the RTL by the designer in a hand-placed fashion. For example, there are big boot multiplexers — big compressors and 16-bit muxes and multipliers that they are starting to add in to reduce the overall size of the design. That reduces the number of routes that you necessity to make, and as you proceed down in nodes this reduction in number of routes saves a lot of switching power. These things are continuously running and transmitting signals, so as miniature connection as you can get is what really helps rescue power.”
These decisions start up front during the planning phase of the design. But as with any other kind of design, engineering teams are very worried about design timelines and tapeout timelines, and power can Have a broad repercussion on schedules.
“There’s a broad race to promote up with the best neural network processing architecture, and these RTLs hold on changing until pretty much the last month of tapeout,” Rajoo said. “As a result, design teams are very worried about finding [library] solutions that give enough flexibility to modify things down the line. This has risen as a prime consideration for both SoC designers and their design managers who want to Have this flexibility. These teams necessity a breadth of options, especially on advanced nodes, because the number of foundries that are doing the most advanced nodes is down to two, maybe three if you’re being generous.”
Within these unusual architectures, optimization around power is becoming a censorious design element. “Low-power design is not limited to platforms relish mobile or IoT,” said Dave Pursley, senior principal product manager for the Digital & Signoff Group at Cadence. “Computationally intensive algorithms are an gripping problem because the computations themselves will require a significant amount of energy to perform. In other words, there is a fairly tall ‘floor’ when it comes to the amount of energy that will live consumed.”
All of this has pushed the design space well beyond just the hardware to the movement of data through a system, including what gets processed where, how precise the computation needs to be, and how it is stored and read in memory.
“Theoretically, from a dynamic switching perspective, the lowest energy solution to compute an algorithm would live to compute it as in as few clock cycles as viable and then shut off via clock gating—or better yet, via power shutoff,” Pursley said. “That minimizes the amount of ‘unproductive’ switching, such as muxing, flip-flops, and the amount clock-switching but that often is not the best tradeoff, because the required silicon district would live larger. That, in turn, increases costs, leakage, and even dynamic energy due to the higher capacitance of longer interconnects. Moreover, it may not even live feasible, especially for computationally intensive algorithms. Power is energy over time, so computing an energy-hungry algorithm in a short time may live infeasible or too costly from a power perspective.”
In these cases, it is the chore of the designer and the EDA tools they utilize to amortize that energy over time. The goal is an acceptable power profile with minimal energy overhead, while noiseless meeting the performance requirements of the application. So while RTL and physical optimizations can reduce power by 20% or more, the most Important optimization begins with a power-efficient RTL architecture. That includes an understanding of the clock speeds of the various blocks, how they communicate with each other, what is the recollection architecture and the throughput, and what is the overall power repercussion of the architecture. Modeling any of this remains difficult, however, largely because so many of the applications and architectures are new.
“With finFETs, with self-heating behavior, they Have some history from the earliest finFETs,” said João Geada, chief technologist for the semiconductor business unit at ANSYS. “This is the fraction that concerns me the most. They are making parts for which they don’t really Have history on the modeling side on the foundry. They Have the simulation technology. If they Have the models — both on the highly circumstantial stuff, as well as on the large-scale chip-wide stuff on their side. They achieve necessity both, but they depend critically on models, and that’s noiseless a very challenging area.”
Still, the power problem is so big and diffuse that some higher plane of abstraction is required.
“In many cases, the best artery to figure this out is to utilize high-level synthesis (HLS) to actually create multiple RTLs with different architectures and actually measure the power with realistic stimulus,” Pursley said, noting that state-of-the-art RTL power estimation tools today can produce power estimates within 15% of sign-off. “The actual trick is to ensure you Have realistic stimulus for measuring power. For example, for a processor the ‘boot Linux’ test is noteworthy for functional testing and peak power analysis, but it is likely a terrible metric for optimizing mediocre power to maximize battery life. A better stimulus would live the processor running its typical applications. It is Important to utilize the redress stimuli, or windows of stimuli, for the redress optimization tasks. Otherwise, you or your tools will live making optimization decisions based on tainted data.”
If the stimulus is known to live representative, it can furthermore feed into the implementation tools to ensure that the identical power goals and tradeoffs are being made throughout the flow. Introducing or changing stimuli late in the flux increases the desultory of a non-convergent optimization flow, or at least one that takes longer to converge.
Then, as early as RTL synthesis, multi-mode, multi-corner (MMMC) optimization should live used, he said. That allows RTL physical synthesis tools to create power-optimized netlists, which involve well-balanced logic to avoid glitching, optimal leakage optimization, advanced clock gating, multi-bit cell inferencing, and power-aware design-for-test.
“Like the architectural optimizations, these types of implementation optimizations Have the most repercussion on power when introduced early in the flow,” Pursley said. “Introducing MMMC in layout or signoff changes the optimization goals partway through the flow. At best, this means that optimizations done by RTL synthesis were wasted and may live undone. At worst, you now Have a flux that will grasp many iterations to converge through signoff, with an increased desultory of a costly re-spin due to error-prone manual iterations.”
Methods for reducing power at RTL and below — power gating, clock gating, multi-Vdd, multi-threshold, DVFS — are well understood. The problem is that by the time RTL is available, the project is already well advanced and it’s too late to get any bigger changes, said Tim Kogel, principal applications engineer at Synopsys.
The biggest repercussion on power, energy, heat, and cost is achieved at the system level, and it works best when the design team has circumstantial learning of the suspension application and utilize cases. That allows engineers to group components into power domains that can live powered down as much as possible, as well as to define power management policy and operating points for DVFS. It furthermore helps to figure out the best artery to dole workloads to processing and recollection resources to remain within power and thermal budgets.
“The power needs to live considered and optimized well before RTL availability, at the architecture specification phase,” said Kogel. “The problem is that accurate data about the power consumption is typically not available during architecture specification phase. At best you Have some data-sheet numbers and data from previous projects. It becomes worse when you try to roll up that premature data in spreadsheets because you are missing the dynamic result of the application utilizing different components at different points in time. Even if the hardware implementation has been designed for low power, the efficient power consumption is often much higher than expected because the software does not leverage the low-power mechanism provided by the hardware. Thus, a minuscule oversight from the software developer can prevent a power domain from being shut down.”
To enable early power estimation, IEEE 1801 UPF has defined a yardstick format for system plane power models. “This artery UPF power monitors can live added to architecture models and virtual platforms for software development,” Kogel said. “Architects can analyze and optimize power based on the actual activity, and software developers become alert of the repercussion of their software on power consumption. Even if the power data is not accurate, trend-based analysis based on the simulated activity provides valuable insight. Later the initial power data can live refined as more accurate measurements become available.”
While characterization of system-level power models remain a challenge, it’s viable power characterization tools could live enhanced to generate system-level power models.
Power matters moreThere has never been a more pressing necessity to impregnate about the power in chips as today because of the rapid surge in data generated by the proliferation of connected sensors and devices.
“In the days of PCs where the source of power supply used to live 220V AC, it was any fine,” said Mohammed Fahad, product specialist at Mentor, a Siemens Business. “But with the advent of handheld devices relish smart phones and tablets, it’s not just that the geometries of the computing devices Have shrunk. The devices are getting loaded with more and more apps and services. Possibilities to fabricate chips at smaller nodes Have enabled the chipmakers to pack billions of transistors on even smaller silicon real-estates. With enormously involved logic going into even tinier chips, the power consumption is getting on the censorious path and often causing chips to burn out. Industry research has found that power is the second most frequent understanding for chip re-spins. Billions of dollars in investment are going down the drain. This is why design companies today Have a very robust low power methodologies in place, built around sophisticated power estimation and optimization tools.”
Performing power estimation is about knowing the power scenario of the chip. Designers would relish to understand the overall power consumption of their blocks, where the hotspots are, and which areas are overshooting the budget. In other words, where is power being wasted? If power consumption of the chip stays within the budget, it’s any pleasant news. But what if it doesn’t?
Fahad famed that RTL power estimation tools define a problem statement for the RTL power optimization tools to address it, identify the computational redundancies in RTL, and inform the user how these redundancies in the code could live eliminated. Tools furthermore provide ways to automatically fix these redundancies and write out the power-optimized RTL. “Optimizing the RTL for power early in the design stages pays higher dividends than engaging later in the cycle. Therefore, low-power methodology demands that power optimization should live eschew well before the code freeze so that it is easy to get any power-saving code changes at the RTL or architectural level-if necessary.”
There are various ways in which a chip’s power consumption can live reduced or controlled, including gating the non-observable operations on flops and memories, stopping the design toggles for stable inputs and outputs and bypassing the stable recollection accesses. At the architecture level, changing the shift register operations to circular buffer, and finding a common gating condition for blocks rather than just flops furthermore can help.
Fundamentally, the key to efficient power management, from the smallest battery-operated IoT devices to the hungriest GPU and SoC designs, is drawing only the power that is really needed. Different functions on a chip should eschew at the lowest voltage and clock hurry that can deliver the required performance, while functions not currently in utilize should live on standby or turned off entirely. To accomplish this, involved chips Have dozens or even hundreds of power domains, each of which controls the operating situation for a portion of the design.
The rules for how these domains can live manipulated are usually quite complex, and iterating through any viable legal power combinations in simulation is impractical. One solution to finding and fixing potential problems may require applying existing tools in unusual ways.
“Rules for which power domains should live on or off depending on what the chip is doing can live captured in the profile of assertions,” said Tom Anderson, technical marketing consultant at OneSpin Solutions, noting that formal can prove that only legal combinations of power domain settings are possible, or generate tests showing violations if there are bugs in the design. “Formal verification can prove that these rules are satisfied under any conditions or report bugs. Finding and fixing power-related issues pre-silicon is censorious to avoid a chip that doesn’t work because key functions are powered down, or one that suffers thermal breakdown when too much of the chip is turned on at the identical time.”
For this, power estimation isn’t enough. “It’s not that they shouldn’t achieve anything at the RTL,” said Madgy Abadir, vice president of marketing at Helic. “You can eschew some RTL power estimation and achieve things relish that, but it is not sufficient. Anything you can achieve to better on your design at the RTL is always a plus, but it’s not going to live the plenary answer. Especially at the physical level, there are phenomena such as thermal and electromagnetic effects, and these effects can only live seen once the layout is complete. Once you Have the actual physics, such as the IR drop, analysis needs to betide on the actual physical layout that you are planning to implement. Only when you perceive the effects can you resolve if it is acceptable or not. This is not something that can live characterized early on and just achieve it in a library.”
Especially for high-power-consuming chips relish GPUs, a lot depends on the application that is running.
“When people develop GPUs, it’s relish developing a microprocessor in the musty days,” Abadir said. “They don’t know exactly what applications people will live running, and it is general-purpose. There might live many, many customers and applications that would change over time. It may grasp a pair of years for that to gather developed from the time it’s in RTL to the time it is on the shelf. During that time a lot of software gets written, a lot of apps will live developed. The algorithms are where the optimization needs to happen, and some of it depends on what kind of algorithm you necessity to live running. If you’re doing pattern matching or if you’re doing sorting or searching, there are many different ways of executing these types of tasks. Every one of them has a different power, a different performance kindly of characteristic. Depending on what you’re trying to achieve and how pleasant your software developers are, at the suspension of the day, this is what determines the actual power consumption of the task.”
This is where learning of the suspension application really helps. “If I am developing a GPU and Have learning of the kind of application that would eschew on my chip eventually, which in a lot of cases people do, they try to achieve performance modeling and power modeling in the early stages to figure out the architecture — which kind and what to do,” he said. “When it comes to power, it’s a very difficult problem. The problem is how to estimate power at the tall level. Some approach this from a characterization point of view, which means you characterize gates and cells, the worst case for timing and for power. But in many cases, such as with GPUs, we’re doing things that Have not been done before. Where achieve you gather the models? We’re estimating at the tall plane how much power is required, and this can live a guessing game because it’s not accurate and can live artery off from what happens with the actual chips. This is because the actual power consumption has to achieve with the actual physical attributes of the chip.”
Another significant factor is the option of algorithm. There may live several different sorting algorithms, for example, each of which may eschew at a different hurry or Have different recollection requirements. The tradeoffs here can Have a broad repercussion on how much power is used, though.
“As a developer of the chip, at the RTL what achieve I do? I developed the GPU that can add and multiply, proceed through recollection and gather things to operate in parallel, Have multiple threads,” Abadir said. “Most of the techniques for lowering the power promote in the implementation stage for these kind of chips, so doing it early requires control of the application. I necessity to control the algorithm. ‘Early’ means the keys are in the hands of the software people. ‘Later’ means the keys are in the hands of the hardware people. It might live both of them operating in hardware-software co-design, but later on somebody will pick the algorithm, and now the hardware guy needs to tweak any the viable things that are clock gating.”
ConclusionThe semiconductor industry is coming to grips with the fact that general-purpose chips are no longer the path forward. The unusual currency is data, and processing that data quickly with blazing hasty throughput and access to recollection are key design elements.
But making this betide without burning up a chip is a massive and growing challenge, and it’s only getting harder as the volume of data increases and the benefits of device scaling decrease. Power is the main gating factor, and it’s becoming much more difficult to fix as compute architectures and claim for processing continue to rise.
Power Modeling And Analysis
Taming NBTI To better Device Reliability
Designing For Ultra-Low-Power IoT Devices
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